1. Technical Field
Embodiments of the present invention relate to a memory device, and more particularly, to a memory device capable of communicating with hosts at different speeds, a data communication system using the memory device, and a memory device that communicates with a host at different speeds and manages access to shared memory.
2. Discussion of Related Art
Due to the diversification in application environments of memory devices, and the increasing capacity and speed of memory devices, the data transmission speed and data throughput between hosts, such as memory controllers, and memory devices, continues to increase as well. With increased transmission speed and data throughput rates, it becomes more challenging to ensure the signal integrity of data transmitted and received to and from these memory devices.
In data communication, since data reception and transmission speed influences the topology of connecting hosts with memory devices, a limitation exists in the number of Dual In line Memory Modules (DIMMS) which each channel can support in a system requiring a high capacity memory. In order to remove the limitation, a FB (Fully Buffered)-DIMM structure is adopted.
FIG. 1 is a block diagram of a conventional memory device 100 including a high speed port interface (HSP I/F) 110.
Referring to FIG. 1, the memory device 100 includes a high speed port interface (HSP I/F) 110, a high speed data communication block 120, an operation setting block 130, and a control logic 140.
The high speed port interface 110 includes a high speed port 111 and a high speed data input/output circuit 112 to perform an interface function of communicating with a host at a high speed. The high speed port 111 is a pin of the memory device 100, and the high speed data input/output circuit 112 performs data synchronization between the host and the high speed data communication block 120.
The high speed data communication block 120 is used for high speed data communication, and includes functional blocks 121, a data interface 122, and a memory cell 123.
The operation setting block 130 includes a Phased Locked Loop (PLL) 131, a temperature sensor 132, and a status register 133, to control the operation of the memory device 100.
The control logic 140 controls the operations of the high speed data communication block 120 and the operation setting block 130. Data can be input to or output from the control logic 140 directly through the high speed port interface 110 or through the high speed port interface 110 and the functional blocks 121.
A memory device for FB-DIMM includes a buffer. In FIG. 1, the high speed port interface 110 corresponds to a buffer. Control signals and data signals used for data communication between a host and the memory device 100 are received or transferred through the buffer 110. In order to improve the performance of a system with a FB-DIMM structure, it is necessary to increase the data reception/transmission speed between the host and the buffer 110, between the buffer 110 and the high speed data communication block 120, and between the control logic 140 and both the high speed data communication block 120 and the operation setting block 130 of the memory device 100.
However, control signals and data signals do not necessarily need to travel at high speeds between the memory device 100 and the host. For example, when data having information regarding operation setting conditions of the memory device 100 is written to or read from a predetermined area of the operation setting block 130 of the memory device 100, the accuracy of the data is more important than the speed at which the data is written or read.
The information regarding the operation setting conditions of the memory device 100 may include operation mode, temperature sensor status, and error flags. Information regarding operation setting conditions of a memory device is essential for memory devices engaged in high speed data communication.
The high speed data communication block 120 includes a plurality of functional blocks for interfacing. For example, the high speed data communication block 120 includes interface functional blocks corresponding to the number of signal lines required for high speed data communication, and interface functional blocks required for receiving or transmitting data from or to the operation setting block 130.
The high speed port interface 110 interfaces with the high speed data communication block 120. This means that there is a dedicated interface for handling the input and output of high speed communications. However, such a dedicated interface occupies a large area on a circuit and can often have a high rate of power consumption. Therefore, it is inefficient in terms of layout size and power consumption to use an interface dedicated to high speed communications to write or read information that does not require high speed communication.
Thus, there is a need for memory devices that can communicate with hosts at different speeds. However, such a host may attempt to access a same memory bank of the memory device at the same time. Thus, there is a further need for a memory device that can communicate with hosts at different speeds while managing access to shared memory.